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Altera_Forum
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13 years ago

Managing input on the FPGA board

Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also teste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Yes, exactly. ADC is also 14 bits

I have to detect certain patterns of 5 pulses(every pulse have close to 25 samples) from the continuous streams of input coming from ADC and as soon as this pattern is detected I have to store the input data starting from that detected point. I have also attached the simulation here for clarification.

Note: in this simulation, only 512 input is considered instead of 1099 I mentioned above.

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Once you detect the pattern then you save input data?? for how long and what to do with it? It is the subsequent processing that determines why and how much you save.