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Altera_Forum
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13 years ago

Managing input on the FPGA board

Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also teste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hello, thanks for the reply first.

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If your signal is from ADC then you process it as it comes.

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Yes, My signal is from ADC (daughter card: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=278) to FPGA pins.

Does it mean that it repeat/reset automatically as soon as number of input reaches to maximum defined limit in the program (e.g. in my case 1099)?

and it works even the input is more than 1099 samples?

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If you have to store it at some point then you can use memory defining how much storage is required.

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Could you please provide a short description/example for this?