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Altera_Forum
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13 years ago

Managing input on the FPGA board

Hello, I have following kind of input in my VHDL Program: type binary_array is array(0 to 1099) of std_LOGIC_VECTOR(13 downto 0); I run the Program successfully in Quratus and also teste...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

My suggestion would be to consider using the in system memory content tool. You could add a VHDL/Verilog module to wrap around a RAM, and using this RAM to be your stimulus/response. -James