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Altera_Forum
Honored Contributor
Honored ContributorM20k block configuration
Hi all! I'm new to OpenCL and the FPGA world in general and I'm just starting to grasp how to properly use M20K blocks for parallel accesses. Since I need very many of them over several arrays t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Since every Block Ram has two physical ports, respectively for R/W, I am in the situation where one of the variables needs to be read and the other one updated, so that the total number of accesses is two. Merging variables into the same block would have provided a good deal of saving. --- Quote End --- Actually you can effectively double the number of ports by double-pumping the Block RAMs; however, the compiler usually does that automatically. I am not sure what you mean by "one of the variables needs to be read and the other one updated"; every variable will have at least one read point, and one write point in every kernel and hence, without double-pumping, there is no way two variables can share one Block RAM without port sharing. --- Quote Start --- I'm disappointed they actually introduced that in the doc. without implementing --- Quote End --- They have definitely implemented it, but likely in Quartus v17.1. It is not going to work with earlier versions.
