Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHu jimbo,
thanks for your answer. Okay, now when I use those commands directly in the TQ console, they work . . . Now, I got some output to examine why this signal is determined as a clock. It feeds some onchip rom memory WE signal. Which should be also constrained by QSYS, shouldn't it? Okay, i have to dig a little deeper into this. The clock constraint for 50MHz (which indeed has a period of 20ns) was an approproate choice, I suppose. However, after re-compiling and re-running TQ, it reports a FMax for that clock of 437.64 MHz which it says is "limit due to minimum period restriction (tmin)". I'm still wondering why i have to care about internal QSYS timing constraints. maybe someone can explain? Regards, Maik