lvds simulation of stratix 4 using cst design studio

Hello,

In attachment you can find a printscreen of my simulation setup, and results.

I used the ibis model (lvds25_ro_p0_v0) of the stratix 4 downloaded from the site.

The excitation signal of port 1 is a pulse of 50Mhz 2.5V in amplitude.

I connect the output of the ibis model to a 50R termination resistor to ground.

I would expect an output wave of 1V to 1.4V, because these are the levels of lvds (of one single ended net)

But as the graph shows, I get an output of approx. 0 to 1V.

So my conclusion is that there is something terribly wrong in my setup :-)

and I can't figure out what it is.

Any suggestions?

Thx,

Tim