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RPDM's avatar
RPDM
Icon for Occasional Contributor rankOccasional Contributor
8 years ago
Solved

LVDS SERDES reference clock enforcement change in 18.1

Hi, In Quartus 17.1 & 18.0, on an Arria 10, I was able to use a Dedicated Transceiver Reference Clock to feed the PLL used to generate some LVDS outputs. In 18.1, my existing design generates an er...
  • JosephC_Intel's avatar
    JosephC_Intel
    8 years ago

    Hi Richard ,

    What being communicated by Anand on October 10, 2018 is correct. We've been discussed internally back and forth regarding this inquiry. At design perspective, we do not encourage to use TX ref clk for LVDS SERDES. Quartus II Tools should have and had to blocked this setting even in earlier version released.

    So, what being captured in Table 9 in LVDS SERDES Guide is determined on how this operational setting going to works. Any standalone interfaces less than 23 channels required a refclk pin in within the same IO Bank whereby for those interfaces that consist of more than 23 channels, we would recommend to use channels 23-71 for refclk input sharing.

    On the other hand, we are working on a fix on future release (Tentative) to have more error checking. This will make sure users isn't using the clock from another IOPLL or some other sources from IO Bank.

    For your PCB design, we would recommend to used Quartus V18 if this suite yours product or change your design based on later Quartus LVDS SERDES characterizations. Otherwise, this options will not be allowed from Quartus V18.1 and onward.

    I hope this addressed yours doubt and thanks for using this forum to get support.

    Thanks,

    Joseph

    Intel Customer Support

gof00's avatar
gof00
Icon for New Contributor rankNew Contributor
7 years ago

Also the simple socket server reference/example design from intel fails on Cyclone 10 GX dev kit board (from Terasic) even if all clock and all serdes pins are located in the same bank as this error message request.

By default the simple socket server reference/example design for Cyclone 10 GX has two clocks. 125 MHz reference clock for PCS and 50 MHz clock from another bank (for the rest of the design).

You can simplify the design by driving all clock from one clock via iopll. But even if you generate 50 MHz clock by pll from 125 MHz dedicated clock input it still doesn't fit:

Error(18694): The reference clock on PLL "sss_qsys_inst|tse_0_tse|tse_mac|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll",

which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

It's the clear bug that can be easily reproduced when you try to compile the reference/example design in something newer than 18.0 pro.