LVDS_RX LVDS_TX with Quartus 13.1 on Cyclone V

Hi all,

I'm trying to implement an LVDS_RX/TX on my Cyclone V with Quartus 13.1.

When I compile the project Quartus give me this error:

"Error: IR FIFO USERDES Block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:ALTLVDS_RX_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'WRITECLK' port. It must be connected to one of the valid ports listed below. Info: Can be connected to LOADEN port of arriav_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of generic_pll WYSIWYG Info: Can be connected to LVDSCLK port of cyclonev_pll_lvds_output WYSIWYG Info: Can be connected to OUTCLK port of arriav_clkena WYSIWYG"

I found this page that tell about this error:

http://www.altera.com/support/kdb/solutions/rd02152013_340.html

and this other page where there are some sample projects for solve the problem:

http://www.altera.com/support/kdb/solutions/rd04102013_389.html

In this sample projects there is a component "cyclonev_pll_lvds_output" thet I don't understand what is and how works.

Also there isn't a VHDL file with the architercure of the component.

can anyone help me to implement this component?