lvds outclock divide factor

Hi All,

I have a specific question regarding the LVDS TX and LVDS Rx megafunction. I am sharing pll's between the tx and rx. I am trying to get the lvds outclock datrate and clock frequency to be the same basically have a divide factor "B" of 1. But the GUI has no option to for 1, i can choose between 2,4, 10 and 20.

Basically i am trying to achieve the function below

90 Mhz- clock - LVDS Rx - 9 Mhz Parallel clock

Serial data 1 bit - - 10 bit parallel data

(Deserialization of 10)

90 Mhz clock out - LVDS Tx - 9 Mhz parallel clock

Serial data 1 bit - 10 bit parallel data

But in the Tx block i have the option for "outclock divide factor "B" of 2, 4,6, 10 or 20 available. I do not want to divide the outclock by 2. I would like to keep the clock and data rate the same (90 Mbps, 90 Mhz)

Is there any way to achieve this ?

I am using Quartus 12.1

Thanks,