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Honored ContributorLVDS on GX transceiver error: "Impossible to choose a legal VCCIO value"
Hello,
I am trying to use a Cyclone IV GX Transceiver as an input for LVDS signals. My target device is EP4CGX150CF23C7 and I am working with Quartus II 11.0 SP1 (Windows). When I assign "LVDS" as I/O Standard for any of the differential transceiver input pins (e.g. GXB_RX0n/GXB_RX0p - Y1/Y2) and then compile my design, the fitter fails with the following error messages: --- Quote Start --- error: I/O bank QL0 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank info: Can't select VCCIO 1.5V for I/O bank due to 1 input or bidirectional pins info: Input or bidirectional pin rx_datain[0] uses I/O standard LVDS error: I/O bank QL0 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank info: Can't select VCCIO 1.5V for I/O bank due to 1 input or bidirectional pins info: Input or bidirectional pin rx_datain[0](n) uses I/O standard LVDS --- Quote End --- However, LVDS should be supported according to Cyclone IV Device Handbook Vol. 2 Section 1-10 Table 1-2 "electrical features supported by the cyclone iv gx receiver input buffer". The remaining pins of bank QL0 are empty and no additional I/O standards have been selected for any QL0 input or output other than LVDS on GXB_RX0n/GXB_RX0p. For testing purposes I created a blank project with nothing but one instance of the ALTGX megafunction and a single input pin pair "rx_datain[0]/rx_datain[0](n)"; the issue still remains the same. Why is the fitter trying to select VCCIO 1.5V at all? On all other banks, 2.5V is the correct VCCIO to be used with LVDS. Is this a Quartus II error or am I missing something?
