LVDS Assignment in Quartus

Hello Jatinp,

I checked your results in Quartus simulator, cause I have no Stratix III board available. I had a 2x7-Bit deserializer setup, that I used with an AD9259, Cyclone III and derialization in LE. The sample rate is 32 MHz in this case. I changed it to a Stratix III 7-Bit LVDS receiver with this Megafunction parameters:

common_rx_tx_pll => "OFF",
deserialization_factor => 7,
enable_dpa_mode => "OFF",
implement_in_les => "OFF",
inclock_data_alignment => "UNUSED",
inclock_period => 31250,
inclock_phase_shift => 0,
input_data_rate => 448,
intended_device_family => "Stratix III",
lpm_hint => "CBX_MODULE_PREFIX=RX",
lpm_type => "altlvds_rx",
number_of_channels => 4,
outclock_resource => "AUTO",
registered_output => "OFF",
use_external_pll => "OFF",
rx_align_data_reg => "RISING_EDGE"

I found, that the input data had to be delayed by 4 bitclocks to get correct word alignment.

I understand that your results are also from simulation. Have you the opportunity to validate the alignment with Stratix III hardware?

I have been using hardware SERDES before with Arria GX, but in a design with DPA. So the word alignment was achieved automaticly without thinking about it.

I suspect, that Stratix III LVDS receiver may require some pulses at the data_align input to achieve the specified alignment of LVDS frame with inclk rising edge. Another option is to use an external PLL and specify an appropriate phaseshift for the LVDS clocks. The inclock_phase_shift in LVDS receiver Megafunction has an adjustment range of a bitclock interval only. But you can see in PLL parameters report, that the Megafunction is using a multiple bit clock phase shift for the internal LVDS slow clock.

Regards,

Frank