LVDS Assignment in Quartus

As previous posts said, it is OK to have only the "p" leg of a differential pin pair in the source file and let the Fitter automatically create the pin for the "n" leg and place it in the correct location. However, you have the option of including both the "p" and "n" legs in your source file for Stratix III and Cyclone III. Here is the Help page for the primitive that lets you do this with input pins:

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ALT_INBUF_DIFF Primitive

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The ALT_INBUF_DIFF primitive allows you to name and connect positive and negative pins when a differential I/O standard is applied to an input pin. This primitive allows you to do the following:

Make a location assignment

Make an I/O standard assignment

Enable bus-hold circuitry

Enable a weak pull-up resistor

Make an on-chip termination (OCT) assignment to an input pin from a lower-level entity

This primitive is available for Cyclone III and Stratix III devices only.

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Verilog HDL Example Instantiation:

module test_inbuf_diff (in, in_n, out);
input in,in_n;
output out;
ALT_INBUF_DIF inst1(.i(in), .ibar(in_n), .o(out));
defparam inst1.io_standard = "LVDS";
defparam inst1.location = "IOBANK_1";
defparam inst1.weak_pull_up_resistor = "off";
defparam inst1.enable_bus_hold = "off";
endmodule

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