Honored Contributor
Honored ContributorLVDS I/O are usually represented by one signal in ports and pin assignments, the positive pin is assigned acting for both. The negative pin is assigned automaticly by the fitter.
LVDS I/O with Startix III is connected to dedicated SERDES hardware, but it can be bypassed. I didn't try, but I assume, it can be done by simply acessing the input in regular logic directly rather instantiating a LVDS receiver. To receive 12 Bit serial data, it's possible to use the SERDES hardware as well. e. g. by receiving 2 x 6 bit with double word rate and multiplexing the data to 12 bit. The dedicated LVDS receiver would use the source frame clock only and generate the bitclock from a PLL. This gives more flexibility in adjusting the clock phase than using a fixed bit clock. Lower LVDS rates up to 600 MHz could be also received through DDIO (double data rate) registers, as done in Cyclone series, that has no dedicated SERDES hardware. By utilizing an ADC custom or test pattern, the LVDS phase could also be adjusted with DPA. This may be interesting particularly for higher LVDS data rates.
