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Altera_Forum
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10 years ago

LUT for ADDER

Hello, I make a code VHDL to create a 12 bits Adder. 12 bits adder consists of 12 1 bit Adder has 3 inputs and 2 outputs so we need 2 LUT each one 3 inputs to create 1 Bit Adder. so 24 LUTs f...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

you mean you instained 12 full-adders . are you adding a constant signal? so the quartus turn on normal mode for le <- you out is optimized.

try to turn on arithmetic mode fo le. you can do it from code if you add with non-constant driver, or can you use resource editor in techology map?