Honored ContributorHi,
I am trying for logic equivalence using Formality tool. Synthesis: Synplify_premier While running formality checks, I am getting error that LPM_MUX component not found. I tried searching verilog file in Altera installed path but could not locate. Can you please share path for lpm_mux verilog file? Rgds, Parag+
Honored ContributorSynthesizable lpm_mux implementation used by Quartus is a AHDL file, lpm_mux.tdf, under libraries\megafunctions. In this case, I doubt Formality can read that file. You might want to try to write your own version or use the simulation model from Quartus, which can be found in 220model.v under eda\sim_lib.
I am curious about your motivation of using Formality and experience with it. Would you like to share? I cannot think of good reason to use such tool in the FPGA development flow myself.
