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Altera_Forum's avatar
Altera_Forum
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13 years ago

Low Pass Frequency Filter in Verilog

Hello, I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code: module filter(clk,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Well let me have a go at it in vhdl off my head(not tested) assuming sine phase starts at 0:

let count be binary of suitable width e.g. 20 bits free running i.e. donot stop at 64000-1 


process
begin
wait until clk = '1';
count <= count +1;
sign_bit_d <= sign_bit;
if sign_bit /= sign_bit_d then
    count <= (others => '0');
    mute <= '0';
    if count < 64000-1 then
       mute <= '1';
    end if;
end if;
end process;
output <= input when mute = '0' else (others => '0');