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Altera_Forum
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13 years ago

Low Pass Frequency Filter in Verilog

Hello, I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code: module filter(clk,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I haven't done verilog for years but in vhdl I will do this:

clocked process:

--run counter 0 @ 64000-1;

sign_bit_d <= sign_bit;

output <= input;

if sign_bit /= sign_bit_d and count < 64000 then

output <= (others => '0');

end if;

end process;