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Altera_Forum
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13 years ago

Low Pass Frequency Filter in Verilog

Hello, I am trying to implement a low pass frequency filter in Verilog. I know that the input is a sine wave that oscilates around 0. The threshold is 500hz. Here is my code: module filter(clk,...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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Thanks kaz... though, can you please explain what is the disadvantage of checking the whole period of the input instead of checking only one half?

Thanks

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just to save on counting. Either way it works. It is also much easier to check is sign bit changed value relative to previous value.

than to check if sign bit changed then changed back.