Looking for advice on using OpenCL FPGA for data acquisition

Hi Mscharrer,

Thanks very much for your reply!

It's great that the FIFO issue can be dealt with by the SDK.

Regarding interruptions or control signals, what I'd like to have is a way for the host and the kernel to interactively communicate with each other during the execution of the kernel. For example, when the host is notified that FIFO has the data ready, it will start pulling data from FIFO. Meanwhile, if the kernel is notified that the host has finished reading data, it will resume buffering new data. Did you mean that such notifications are realized by some kind of global memory that can be accessed by both the host and the kernel?

I have some experience with high level programming languages like C++ and Java, but new to FPGA and have no experience with VHDL/VERILOG. That's why I was wondering whether OpenCL would give me an easier jump start than learning low-level HDLs.

Thanks,

Bing