In the past, when quartus could not fit designs, it usually bailed on me after about 8 hours of place and route. I added logic lock regions so I could isolate partitions for timing and close timing on each individually. However, after adding them, p&r has been running for 44 hours. Has anyone run p&r for this long and had a successful result? The logic utilization is about 55%. My main problem is interconnects for the timing.The logic lock regions were set to auto size/location (this is my first iteration). Also, if anyone knows of a nice guide on timing closure with quartus, it would be awesome :D. I've only become frustrated with TimeQuest and chip planner and the altera docs. It's for a Stratix II GX chip.

--- Quote Start --- In the past, when quartus could not fit designs, it usually bailed on me after about 8 hours of place and route. I added logic lock regions so I could isolate partitions for timing and close timing on each individually. However, after adding them, p&r has been running for 44 hours. Has anyone run p&r for this long and had a successful result? The logic utilization is about 55%. My main problem is interconnects for the timing.The logic lock regions were set to auto size/location (this is my first iteration). Also, if anyone knows of a nice guide on timing closure with quartus, it would be awesome :D. I've only become frustrated with TimeQuest and chip planner and the altera docs. It's for a Stratix II GX chip. --- Quote End --- I assume that your first ( 8hours) was without any partition or logiclock setting. The long P&R run with a utilization of 55% indicates, in my point of view, that you have a routing problem in your design. Do you have large multiplexer or special requirements for memory ( bit enable) in your design ? What do mean with "My main problem is interconnects for the timing" ?

Of the 8 hours, how much is placement, how much is route time, and how much is physical synthesis(if you have it on)? This can be found in the messages of the .fit.rpt(I would like these to be broken out more clearly...). If physical synthesis is on, it generally runs twice, so you'll have two sets of messages, and it's total time is usually a part of the total placement time, i.e. if physical synthesis is 3 hours and placement time is 4.5 hours, then only 1.5 hours is really spent placing. If you post the few lines from the .fit.rpt that say how long stuff runs for, that might help. (Also look at the physical synthesis messages on if they help, i.e. if combinational resynthesis improves the design by 0ps, then it's not doing anything besides chewing up compile time). With a better idea of where the time is spent, it would help devise the best way to attack it. Also look at the Tools -> Advisors -> Compile Time Advisors If it's only 55% full, can you put the Fitter Resource Usage Summary section of your report into a .txt file and attach it? That seems awfully low to be having problems, but 55% is a single number, when the fullness of a device really has many factors. What version of Quartus II are you using? Finally, auto-sizing, auto-placing LLRs generally does not work out well. It's generally going to give worse results than a flat compile, which you're seeing, and generally is useful only as a starting point. Note that I don't think there any really good "auto-floorplanning" tools. Synplify's Amplify is a manual tool. Xilinx's Plan Ahead is manual. ASIC tools, as far as I know, are all manual floorplanning tools. From what I've heard, it's one of those things computer's just aren't that good at without spending tons of compile time, while humans tend to be pretty good, especially with intimate knowledge of the design. If you know the DDR2 core is along an edge, then put it in an LLR along that edge. If it then connects to some large procesing block, put that in an LLR next to it. You're basically floorplanning the connections. My experience though, is that it's not an easy thing to do(especially with hierarchies that are imbalanced in resources, i.e. have a ton of memory blocks but little logic, or something like that). Also, what goal are you trying to achieve. A bad floorplan hurts perfromance(which auto-size/floating LLRs will result in bad floorplans with lots of open space). A good floorplan can help by imparting knowledge to the placer on where things should go, how they connect, and limiting the solution space to a good solution, but I don't see huge gains either. If you're way off on timing, it won't have a dramatic affect.

It finally quit after about 55 hours. It apparently maxes out at 100 iterations of region placement, and it took that long to get there. I've given up on the LLR's at this point in time, so fit time is back down to a few hours. It's currently fitting, so I don't have a report to post. Working on improving constraints/going to look at layout ECOs at this point. Some clocks/reset signals had changed in the hierarchy recently, and the assignments didn't get updated so global signals weren't marked properly, nor were some of the other assignments valid. Using Quartus II 8.1.

I've never modified globals as an ECO. Not sure it's possible. Another try might be to copy the project(backup), set the top-level(and only, I assume) partition to post-fit(strict) placement. Make all your assignment changes and rerun. Not sure it will work, but pretty easy since you need to make the assignment changes anyway. And post the info if you want, as Stratix II GX shouldn't have any difficulty fitting a 55% full design.

Hi, I am having the same problem with a design, the fitter just won't come to an adecuate solution. My design has 9 instances of a multiplexer based interconnection structure with 12-32bit 31-to-1 muxes. what do you suggest i do???. I am in the tunning stage of the design so i must recompile a lot of times for small changes. Any help will be appreciated. Thanks in advance Juan Fernando

Long place and route after adding logic lock regions

15 Replies

Altera_Forum
Honored Contributor
16 years ago
I found that the cause for the large fitter times is a huge combinational loop i have into the design, as the design is intended to be made in silicon and this combinational loop is entirely necessary, what should i do to inform the tool that in order to reduce fitting time???

i really need help with this, i need to prototype my design for testing and the design tool is not helping me!!!
Altera_Forum
Honored Contributor
16 years ago
How is a large combinational loop causing long fit times? I'm just curious how the two were correlated, as a long comb loop shouldn't necessarily cause the fit time to go up(yes, the logic of it causes it to go up.) More info on where the compile time is spent is really necessary to make a better guess for solving the problem, since the fitter runs many differnet processes and has different reasons for why compile times could go up. If you want, .zip up your .fit.rpt and attach it, as that provides a lot of information. (I understand you may be sensitive to this and may not be able to...)
Altera_Forum
Honored Contributor
16 years ago
the large combinational loop is tristate communication logic implemented with multiplexers, i've checked by adding registers to the outputs of the logic feeding the communication structure and compile time goes from 1 hour to 2 minutes, somewhere in the handbook is a warning about combitational loops causing the design tools to go into large computational loops, i don't know if this may be the cause of my problem. The current solution that i am exploring is to partition the design leaving the interconection logic out of it and then adding it, but i am kinda new with altera tools so any suggestions will be appreciated.

Thanks for your help
Altera_Forum
Honored Contributor
16 years ago
Many EDA tools take longer time to process (and break) combinational logic loop into implementable logic structures. So, I wouldn't be surprised if Quartus II took a longer time with logic loops in the design.

Knowing how much time was spent in placement and how much time was spent in routing could help pin point the issue much further. Again, do you have any physical synthesis options turned on?
Altera_Forum
Honored Contributor
16 years ago
If you can submit the design, please file a service request at altera.com. That does not sound right, or at least it sounds like something Altera should fix. As sw181 said, I'd be curious if it's in placement or routing, and though it's possible, I'd be surprised if it's directly either. Some other thoughts are that it could be physical synthesis(a portion of placement), as perhaps the re-synthesis algorithm mistakenly loops into an algorithm too deep. Another thought is that the timing analysis takes too long. How long does your TAN/TimeQuest process run at the end? Note that during placement the timing engine is called many, many times to analyze it's current placement. It's a condensed call(i.e. each one is much shorter than the final call), but if some timing analysis loop blew up, that could explain it too.

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Long place and route after adding logic lock regions

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