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Altera_Forum
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9 years ago

Long FIR Filter

Hallo I am using MATLAB and Simulink to create my model and the using the HDL coder to generate HDL code for Altera FPGA. We have a custom hardware made from ep4ce22f17c6n with I2S interface an...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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Hi

the Fs would be 44.1 kHz for now. if possible we would like to go upto 96 kHz but then the filter coefficients are also getting double almost

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if you run a clock @ 100MHz then you have a ratio of 100MHz/44.1KHz ~= 2000 and you can then use MAC i.e. multiply accumulate sharing same mult for 2000 computations. so you will need 5 mults or so