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Altera_Forum
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9 years ago

Long FIR Filter

Hallo I am using MATLAB and Simulink to create my model and the using the HDL coder to generate HDL code for Altera FPGA. We have a custom hardware made from ep4ce22f17c6n with I2S interface an...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi

thanks for the reply. Yes i know that no FPGA has 8192 multipliers. Can you please give me an idea what you mean by the MAC approach.

I tried the attached code, the idea was to break the 8192 taps filter into small filters with 1024 taps. I am using a circular buffer data input and the pass the data through the cascade. But it does not generate code in the HDL coder. I tried loop unrolling and sharing optimizations but no success. If possible please have a look at the attached file.