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Altera_Forum
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9 years ago

Long FIR Filter

Hallo I am using MATLAB and Simulink to create my model and the using the HDL coder to generate HDL code for Altera FPGA. We have a custom hardware made from ep4ce22f17c6n with I2S interface an...
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Altera_Forum
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9 years ago

Pretty drastic filter. It will require large ram (e.g. 8192 *16bits). And no way to get 8192 mults in any basic fpga

If you can clock fast you can use MAC approach.

cascading of a filter is possible but requires Z domain factorisation. You ay also be helped by the principle that h = conv( h1,h2) i.e. a cascade of h1,h2 is equivalent to h