Logic utilization of hello-world vector add

Cyclone V is a very small FPGA, you shouldn't expect to be able to fit a large design on it, even with HDL.

In the particular case of OpenCL, the BSP which holds the necessary IP Cores and logic for host/device communication and the OpenCL runtime uses quite a bit of area on its own, but this amount is fixed regardless of your kernel. In your case, the BSP is probably using 10% of that 15% logic and is actually bigger than the vector add kernel itself.

The input size in host code does not affect area utilization; the only thing that affects area utilization on the FPGA is the kernel code and the BSP.