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Altera_Forum's avatar
Altera_Forum
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14 years ago

Logic gate output from bus

Hello to everybody, I hope I am posting this at the right place. My question is actually very simple. I have a bus, e.g. a[3..0]. And I want to make an OR gate with one output which makes ORs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

for a symbol, you may need to separate out each bit individually and input it into the gate. You can do this by named association

Forget about AHDL (its a dead language)

in VHDL, you can simply use one of the two methods: 


library ieee;
use ieee.std_logic_1164.all; --library used everywhere
use ieee.std_logic_misc.all; --has some useful reduction operations
......
signal a : std_logic_vector(7 downto 0);
signal b : std_logic;
...
b <= or_reduce(a); --also, and, nand, nor, xor, xnor reduce functions

or when Altera finally add some decent VHDL 2008 support:

b <= or a;