Honored Contributor
Honored ContributorI don't have links to examples, but there's a decent amount of documentation on the web, with some searching. If you're not an expert at the Classic Timing Analyzer, I would recommend using TimeQuest just becaue it's the analyzer of the future(i.e. if you're going to spend time, do it with that). It also gives you more tools to analyze specific paths.
If your design is a single clock coming in(and maybe a PLL), then internal timing is probably not a problem. (Any gated clocks?) I/O is interfaces are where timing constraints are the most critical(but also the most difficult to do). Note that you can do a combination of both, i.e. add some debug logic(sometimes it's not too hard to add some checking logic inside your own code and bring it out to SignalProbe. If the data passes, then you know that interface is all right and you move on. Kind of do a high-level search on where the data is bad, and then start narrowing down from there. Once you have a general idea, then start constraining that I/O first, or if it's not a timing issue, dive deeper with debug.
