little change - big mess

Thanks for the fast reply!

@ pletz

I'm using the Quartus II Simulator tool and I did timing simulations.

@ Hua

Yes I got some warnings. But none of them dangerous.

@ Rysc

I'm afraid you are right. Low level debugging will be necessary.

The Design Assistent finds "Combinational logic used as a reset signal" in one case. I will fix that.

Functional simulation shows in principle the correct behavior except for one failure. But this one does not appear in timing simulation.

The results of Static Timing Analysis seem to be uncritical. But if my constraints are wrong this is worth nothing. Do I have to constrain my design using the TimeQuest Timing Analyzer? Till now I made pin assignments using the pin planner and specified my clocks in the individual clocks settings box of the Classic Timing Analyzer - and that worked so far. If this is all I have to do the next task is search and look at the failing signals (using the SignalProbe/LogicAnalyzer Interface approach because I can't use SignalTap with my Web Edition license). If not I have to concentrate on constraining my design at first. Is there any usefull document available that tells how to constrain correct?

Kind regards

Jasmin