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RRomano001's avatar
RRomano001
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6 years ago

Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Linux Qsys Now "platform designer", from old time still has trouble never addressed. ALT_PLL Altera FPGA IP open in a small window with scroll bar, if something is touched in this state after long ...
Serqetry's avatar
Serqetry
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2 years ago

I'm on Quartus Prime Lite 23.1 on Linux, and this ALTPLL Altera FPGA IP module (now called ALTPLL Intel FPGA IP) still does not work. Using the hack mentioned here I can get get the wizard to create it, but I cannot configure it. Any time you get to the (3) Output Clocks page, the wizard crashes. The hack seems to keep it from aborting and deleting it, but there's no way to configure the clocks.

This is a major bummer... it seems to be unusable. If anyone knows how to get around this so the output clocks can be configured... I'd greatly appreciate it.

RGarito's avatar
RGarito
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1 year ago

I'm actually on Quartus Prime Like 23.1 for Windows and the same exact thing happens here (so it's not just a Linux issue).

I applied the modification above (the file was located in C:\intelFPGA_lite\23.1std\ip\altera\sopc_builder_ip\altera_avalon_mega_common )

but it did not help

You can get to the PLL Reconfiguration but when you click Next, the wizard closes and the PLL you were building disappears from the design.