Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Hi ,

I totally understand what you are trying to say, and able to understand the dummy block . My intension only want to show you that the Qsys file is not generated successfully with the design that you send.

Again with Verilog, we had an issue on certain versions between Verilog and VHDL languages . So only to isolate the language issue I have suggested the above procedure.