Linux Qsys Now "platform designer", ALT_PLL Altera FPGA IP doesn't save, crash.

Hi RSree, sorry for what I have to write:

Are you an FPGA designer and proficient on HDl languages, Platform designer usage?

Why I am asking this? I feel as you are VERY far from what happen, from how a PLL work and never checked reconfigure PLL clocks input and PLL section feedback counters.

Issue is about some TCL error I cannot address, Verilog VHDL is just the generated design hardware.

Openiing the design file by hand then set the PLL block, refresh design and then load with all clock, generate correct IP core. Platform designer provided interface DOESN'T WORK!!! INTERFACE, SOFTWARE ISSUE, not HDL generated file.

See snapshot, see what happen to saved PLL has just one clock C0 is on module, where set up C0, C1, C2, input frequency is not 100MHz default MUST BE 50MHz, Optput need be what I select and MORE THAN ONE I repeat REPEAT C0, C1, C2...

Software code messed up is graphic interface, if you open is stretched and if you touch something it crash after a while. Resizing doesn't crash but NEVER save chenges on QSYS file. File is quite messed up.

About dummy Master, this is another point I fear you are far from HDL design, is a very simple useless module to quiet warning and silence bus when no controller are there.

Is very simple to "add new" from left ip core selector one just by new component then import vhdl file.

This missing tcl file ( I can setup on project and send you) is not affecting the culprit of issue YOU CANNOT EDIT NOR APPLY AND SAVE CHANGES TO PLL PARAMETER!!!! THIS FROM 15.0!!