library use clause errors

@tricky:

I am still getting use clause errors. The error below appears if I have a files named basicblocks.vhdl, basicblocks.vhd, d_flipflop.vhdl, and d_flipflop.vhd. All of these files contain a valid entity and architecture of name "d_flipflop". I get the same result if the library directory is empty.

Error (10481): VHDL Use Clause error at tps2834.vhdl(34): design library "basicblocks" does not contain primary unit "d_flipflop"

Lines 34-41 of tps2834 are

u2: entity basicblocks.d_flipflop port map(

clock => not pwm,

preset => '1',

clear => enable,

d => continuous,

q => continuous_sample,

qbar => open

);

Does the definition of "primary unit" exclude entities and architectures? If so, what is an acceptable design unit?

I am aware of the nearly equivalent library design unit dff; I am pursuing this to clear up my understanding of how to create my own libraries.

@Rysc:

This works. It seems that the altera libraries are treated as standard vhdl libraries, but user libraries are not.

Cheers

John