Honored Contributor
Honored ContributorHi vik.vik,
it is unclear what you actually try to achieve. Could you be more specific? --- Quote Start --- what we have done is modified the functionality of basic gates such as AND, OR, etc to meet the requirements of what we want. Lets just call these gates shadow gates. to demonstrate that this idea works i built a simple arbiter using structural verilog. now i want to write an entire processor using that principle (using shadow gates). --- Quote End --- What do you mean by "shadow gates"? Are you intending to prototype some kind of asynchronous architecture based on handshaking protocols? Is it to avoid races and hazards that you specifically want to design up to the gate level? Do you need specific assumptions with respect to signal propagation delays? More info would be welcome to be able to make some suggestions...
