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Altera_Forum
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8 years ago

LFSR doesn't generate random values during simulation Ask

I am new to VHDL. I made this LFSR but don't know why it is stuck between the initial seed value and the other XOR value. I am working with Altera Quartus 16 Lite and ISim. Here is the link https:...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thanks a lot guys I found why it was not shifting. Here is the working part.

temp_out(15) <= temp_out(0);-- shifting bit

temp_out(14) <= temp_out(15);

temp_out(13) <= temp_out(14) xor temp_out(0);

temp_out(12) <= temp_out(13) xor temp_out(0);

temp_out(11) <= temp_out(12);

temp_out(10) <= temp_out(11) xor temp_out(0);

temp_out(9 downto 0) <= temp_out(10 downto 1);