Length Correlation in VHDL

i have here a programme that calculate the correlation of data bits with 8 bits as length in this case i will need for the calculation 4 stage the figure explain the program , so i want to do it with variable length 16 or n for length so can you help plz

library ieee;use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity correla4bit is 
port ( 
         clk : in    std_logic ;
         rst : in    std_logic  ;
         data: in    std_logic_vector(11 downto 0)  ; 
         code: in    std_logic_vector(15 downto 0 )  ;
         Q   :out    std_logic_vector(17 downto 0) )  ;
         end entity ;
architecture arch of correla4bit  is 
       type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;
       type ram16 is array (0 to 3) of signed(15 downto 0) ;
        type Rom is array (0 to 3) of signed(11 downto 0) ;
    
        signal voie :Rom ;
        signal CD    : RAM;
        signal temp: ram16;
        signal sum0   :signed (16 downto 0) ;
        signal sum1   :signed (16 downto 0) ;
        signal AB     :signed (17 downto 0) ;
      begin
     
                                
                            
    CD(0) <= code(15 downto 12);
    CD(1) <= code(11 downto 8);
    CD(2) <= code(7 downto 4);
    CD(3) <= code(3 downto 0); 
    
     etalement:process(clk,rst)
         begin 
                  if(rst='1') then 
                     Q  <=(others=>'0');
                     
                      temp(0)<=x"0000";
                     temp(1)<=x"0000";
                     temp(2)<=x"0000";
                    temp(3)<=x"0000";
                    
                    elsif(clk'event and clk ='1') then 
                   
                        voie(0)<=signed(data) ;  
                        voie(1)<=voie(0);
                        voie(2)<=voie(1);
                        voie(3)<=voie(2);
                        
                        for i in 0 to 3 loop
                           temp(i) <= voie(i)*signed(CD(i));
                        end loop ;
                        
                        sum0<= resize(temp(0),17)+temp(1) ;
                         sum1<= resize(temp(2),17)+temp(3) ;
                          AB<=resize(sum0,18)+sum1 ;
                          Q<=std_logic_vector(AB) ;
                          
                   end if ;  
                                     
                        
                       
          end process ;
 end architecture ;