Length Correlation in VHDL

This is just a standard N tap FIR.

First of all, I suggest you bring in all C co-efficients separately, not as a single bus.

Second, for N taps, you will probably need a package to create the array types to make the design generic.

I dont know why you have declared RAM and ROM types - there is no RAM or ROM in your drawings. They are just arrays of registers.

I would also suggest putting registers after each multiplier and adder stage, or the fmax is going to be very low.