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Altera_Forum
Honored Contributor
8 years agohi, i would like to thank all of you for helping me. i am now able to complete my project all thanks to you all guidance. below is the code is use for comparator 1 and comparator 2
comparator 1: Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comparator is port( q, b : in std_logic_vector( 6 downto 0); c : out std_logic); end comparator; architecture body3 of comparator is begin process (q, b) begin if (q< b +1) then c<='1'; else c<='0'; end if; end process; end body3; comparator 2: Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comparator1 is port( x, y : in std_logic_vector( 6 downto 0); c1 : out std_logic); end comparator1; architecture body3 of comparator1 is begin process (x, y) begin if (x>19) and (x<= 20+y) then c1<='1'; else c1<='0'; end if; end process; end body3;