thank you mr cris72
it's working well
this the vhdl code
library ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY DE0_NANO IS
PORT( LED : out std_logic_vector(7 downto 0);
KEY : in std_logic_vector(1 downto 0);
CLOCK_50 : in std_logic
);
END DE0_NANO;
ARCHITECTURE behavioral OF DE0_NANO IS
signal reset_n: std_logic;
signal counter: std_logic_vector(26 downto 0);
signal PWM_adj: std_logic_vector(5 downto 0);
Signal PWM_width : std_logic_vector (6 downto 0);
begin
reset_n <= KEY(0);
process(CLOCK_50)is
begin
if(CLOCK_50'event and CLOCK_50 ='1') then
if (reset_n='0') then
counter <= "000000000000000000000000000";
LED(0) <= '0';
else
counter <= counter+'1';
PWM_width <= ('0' & PWM_width(5 downto 0)) + ('0' & PWM_adj);
if(counter(26)='1')then
PWM_adj <= counter(25 downto 20);
else
PWM_adj <= not counter(25 downto 20);
end if;
LED(0) <= not PWM_width(6);
LED(1) <= not PWM_width(6);
LED(2) <= not PWM_width(6);
LED(3) <= not PWM_width(6);
LED(4) <= PWM_width(6);
LED(5) <= PWM_width(6);
LED(6) <= PWM_width(6);
LED(7) <= PWM_width(6);
end if;
end if;
end process;
END behavioral;