--- Quote Start ---
if in vhdl i read when bit array counter[26] high or '1' like example below it's that same like if (counter[26])??
if(counter="100000000000000000000000000")then
--- Quote End ---
No. This condition is true if bit 26 is high AND all the others are low.
The vhdl equivalent is simply:
if counter(26) ='1' then
--- Quote Start ---
sub array counter increament every 20 ms if i use counter[26:0] how about the in increment?
--- Quote End ---
I can't understand your question
--- Quote Start ---
I believe this should have been written in a clearer and more correct way:
PWM_width <= { 1'b0, PWM_width[5:0] } + PWM_adj;"
it's 1'b0 = 1 bit in biner the value = 0 and the pwm 6bit logic vector it's pwm width convert to 1 bit or std logic?
--- Quote End ---
This is Verilog syntax. { 1'b0, PWM_width[5:0] } builds a 7 bit vector by concatenating the single bit value=0 and the lower 6bits of PWM_width.
std logic is vhdl specific and doesn't apply to verilog.
Honored Contributor
