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counter[26] is the msb of counter vector.
I guess the process clock runs at 50MHz, then counter[26] continuosly toggles between 1 and 0 at the rate of about 1Hz,
namely when the 26bit counter overflows
i still don't understand about msb counter that have 26 bit
if in vhdl i read when bit array counter[26] high or '1' like example below it's that same like if (counter[26])??
if(counter="100000000000000000000000000")then
how could i make this to vhdl
This is simply to obtain a lower increment period. Compared to the full counter, the sub-array counter[25:20] increments every 20ms
sub array counter increament every 20 ms if i use counter[26:0] how about the in increment?
I believe this should have been written in a clearer and more correct way:
PWM_width <= { 1'b0, PWM_width[5:0] } + PWM_adj;"
it's 1'b0 = 1 bit in biner the value = 0 and the pwm 6bit logic vector it's pwm width convert to 1 bit or std logic?
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