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1."
if(counter[26]) " when condition this active? i don't know value in counter to reach this condition.
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counter[26] is the msb of counter vector.
I guess the process clock runs at 50MHz, then counter[26] continuosly toggles between 1 and 0 at the rate of about 1Hz,
namely when the 26bit counter overflows
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2.
"PWM_adj <= counter[25:20]" why just 25:20 ? i'ts that mean value in array counter[20],counter[21],....counter[25][/I][/I].
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This is simply to obtain a lower increment period. Compared to the full counter, the sub-array counter[25:20] increments every 20ms
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3. "
pwm_width <= pwm_width[5:0]+ pwm_adj;"
in reg/wire declarations pwm adj have 6bit dan pwm width have 7bit, why in just 6 bit in pwm width " + " with pwm adj??
reg [5:0] PWM_adj;
reg [6:0] PWM_width;
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I believe this should have been written in a clearer and more correct way:
PWM_width <= { 1'b0, PWM_width[5:0] } + PWM_adj;"
Verilog is much more tolerant than VHDL regarding type mismatch. Probably the original syntax generates a warning but can compile anyway.
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5.if in vhdl variable counter is defined as std_logic_vector(26 downto 0) right?
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Yes.
Honored Contributor
