Learning VHDL

The sec_clk entity doesnt have a rsts port, but the component declaration inside DigiClock does have a rsts port. Hence you have a missmatch.

This is a good demonstration of why component declarations can cause problems. When the source of an entity is in VHDL, then a component declaration is not needed, and errors like the one that has occured here will be picked up much sooner in the compiler. You can use direct instantiation instead:

c1: entity work.sec_clk port map(clkm,rstsec,sflag);

And some other comments on your code:

1. Positional association in port maps is generally frowned on. It is much easier to maintain, less error prone and easier for others to follow with named association

c1: sec_clk  port map
(clks => clkm,
 ops => sflag);

2. As a beginner, I highly recommend you do NOT use variables. they can cause odd behaviour when you were least expecting it to. Only use signals for expected behaviour

3. Inside a clocked process, NEVER put anything outside the reset or clocked part of the process.

process(clk,reset)
begin
   --- NEVER PUT CODE HERE
  if reset = '1' then
    -- async reset goes here
  elsif rising_edge(clk) then
    -- Logic goes here
  end if;
  -- NEVER PUT ANYTHING HERE EITHER
end process;

4. Do not use any generated logic as a clock, use it as a clock enabled instead and use a single clock for the whole design. Doing so will lead to timing problems.

process(clk)
begin
  if rising_edge(clk) then
    if en = '1' then
      -- logic only activated when enable is set
    end if;
  end if;
end process;

5. Do no mix rising and falling edges in the same design. Stick to a single edge (and conventionally, people using rising_edge). Mixtures of clock edges can make timing much harder

6. Another convention is that active low signals be named something like sig_n or nSig, to make it easier for others to understand it is an active low signal. You have labelled your reset rst, but it is active low. Many engineers would prefer it to be called rst_n. But this leads to another convention - most FPGA engineers like signals to be active high.

7. You only need clk and any async resets in the sensitivity list. Anything inside the clk branch does NOT need to be in the sensitivity list (and could cause simulation slow-down, but this is unlikely nowadays).

8. Comment your code, explaining WHY you have done something that way, not HOW (they should understand the how from the code!)