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Altera_Forum's avatar
Altera_Forum
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15 years ago

Launch and latch times outside of legal time range

Hello all I'm having a strange timing-related message when compiling a VHDL code. Everything was fine in my design (even timing requirements met) until I added a subblock which generates the...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Are those signals are very low frequency clocks, generated by a ripple clock divider?

TimeQuest has limits with very low frequency clocks. IIRC, it's because it uses integers to represent time and analyzing very low frequency clocks (very large periods) involves very large time values.

Solutions are either replacing the very low frequency clocks by clock enables or lying to TimeQuest and specifying not so low frequency for those clocks (ie, 100 kHz)