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Altera_Forum's avatar
Altera_Forum
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15 years ago

Launch and latch times outside of legal time range

Hello all

I'm having a strange timing-related message when compiling a VHDL code.

Everything was fine in my design (even timing requirements met) until I added a subblock which generates these signals (CLK_PIX and HS_CLK). I was not the one who coded nor debugged this subblock, it was tested by someone else.

Both signals (CLK_PIX and HS_CLK) are generated from the same master clock(ABS_CLK), which is a PLL output. The message is the following:

warning: the launch and latch times for the relationship between source clock: hs_clk and destination clock: clk_pix are outside of the legal time range. the relationship difference is correct, however the launch time is set to 0.

And I got a lot of negative slack complaining on Timequest Timing Analyzer. The point is that I could not take this warning off, I'd like at least to fully understand what it means, to have a starting point.

Thanks in advance for your help

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Are those signals are very low frequency clocks, generated by a ripple clock divider?

    TimeQuest has limits with very low frequency clocks. IIRC, it's because it uses integers to represent time and analyzing very low frequency clocks (very large periods) involves very large time values.

    Solutions are either replacing the very low frequency clocks by clock enables or lying to TimeQuest and specifying not so low frequency for those clocks (ie, 100 kHz)