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Do you mean that the multiplexer would wait for the FALSE condition although the TRUE condition execution is completed? Or does multiplexer has a fixed schedule to decide which condition is TRUE?
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No, there is no "scheduling" (in single work-item kernels) or "waiting". The compiler will insert extra registers to make sure the latency of both paths is the same. This is the only way the operation can be pipelined correctly and is one of the most classical FPGA-based optimizations. Refer to slide 68 from Altera's own presentation:
https://cpufpga.files.wordpress.com/2016/04/opencl_for_fpgas_isca_2016.pdf This should also be somewhere in their OpenCL documentation but I didn't find it.
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I have attached the system viewer screenshot of kernel 1 (first post) and kernel 2. It looks like two parallel paths are not created as you told. The two conditions are in serial.
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Since the forum scales down images, I can hardly see anything and I am not sure if the way the system is drawn in the report is accurate enough for this discussion anyway. Furthermore, you are never writing anything to your local buffer and the compiler even gives a warning about this. It could be generating the circuit in a specific way because of this.
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