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Altera_Forum
Honored Contributor
Honored Contributorlatency in 1 port ram help
Hello, I am new to vhdl. I am using the on chip RAM and the built in integer comparator to do something as following: 1. memory_a & memory_b both are the on chip ram with size 32 bit * 128...
Altera_ForumHonored Contributor
Honored ContributorHi,
yes, it is quite common to delay signals to be in sync with others. However, sometimes it's not exactly as obvious as having a delayed signal. Sometimes you just add another state to a state-machine, which equals a single delay. Sometimes you implement a FIFO, so that an uncertain delay can be compensated for. And, needless to say, you're quite happy if you find an alternative solution that works without additional delay :-) Best regards, GooGooCluster
