Honored Contributor
Honored ContributorHi,
yes, there will always be a delay. However, all you have to do is to "disable" the comparator during the time that the data is invalid. That's no particular VHDL trick, it's just a thing you have to get use to when doing hardware (it gets worse with SDRAM chips, where the timing can differ when you hit a refresh cycle...). Here's some example code:library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example is
port(
clk, rst: in std_logic;
test_request: in std_logic;
test_address: in std_logic_vector(6 downto 0);
test_pass: out std_logic;
test_fail: out std_logic);
end entity;
architecture rtl of example is
component my_memory is
port(
address: in std_logic_vector (6 downto 0);
clock: in std_logic;
data: in std_logic_vector (31 downto 0);
wren: in std_logic;
q: out std_logic_vector (31 downto 0));
end component;
signal data_a, data_b: std_logic_vector (31 downto 0);
signal delay1, delay2: std_logic;
begin
my_memory_inst_a: my_memory
port map(
address => test_address,
clock => clk,
data => (others => '-'),
wren => '0', -- never write (memory is pre-initialized)
q => data_a);
my_memory_inst_b: my_memory
port map(
address => test_address,
clock => clk,
data => (others => '-'),
wren => '0', -- never write (memory is pre-initialized)
q => data_b);
process(rst, clk) is
begin
if(rst = '1') then
delay1 <= '0';
delay2 <= '0';
elsif(rising_edge(clk)) then
-- delay request signal
delay1 <= test_request;
delay2 <= delay1;
end if;
end process;
process(rst, clk) is
begin
if(rst = '1') then
test_pass <= '0';
test_fail <= '0';
elsif(rising_edge(clk)) then
-- default assignments
test_pass <= '0';
test_fail <= '0';
-- compare data
if(delay2 = '1') then -- note that delay2 is in sync with the read data
if(data_a = data_b) then
test_pass <= '1';
else
test_fail <= '1';
end if;
end if;
end if;
end process;
end architecture;
