Latches in frequecny divider using fsm implementation

FPGAs do not support dual edge flip flops. Plus Synthesis tools (but not simulators) ignore the sensitivity list of the always block. Hence, if you write:

always @(clk)

The synthesis tool ignores it, and treats it as

always @(*)

This is because synth tools have to infer logic from your code, and have to follow specific templates to generate specific logic.

See https://www.altera.com/en_us/pdfs/literature/hb/qts/qts-qps-handbook.pdf , section 2-12 for recommended HDL coding styles.

The problem with writing

always @(clk)

Is that in simulation it will behave like a dual edge flop, but as synthesis treats it as always @(*), the simulation behaviour and real hardware behaviour will not match. This is why you get warnings about latch generation when you may have a perfectly good simultion.