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Altera_Forum
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8 years ago

Latches in frequecny divider using fsm implementation

I am new to verilog and HDL. I want to implement a N-frequency divider, which count clock ticks (pos and neg) and start the counting mechanism from the first rising edge of the input clk. In a...
Altera_Forum's avatar
Altera_Forum
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8 years ago

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Hi Tricky,

Thank you for your reply.

If I get it right,

always @(clk)

begin

...

end

or always @(*)

are supported for compilation only but not for simulation and programming into FPGAs.

Am I correct?

Thanks

--- Quote End ---

Incorrect.

They are a legitimate way of coding verilog, for creating logic or latches, which are both suitable for FPGAs.