Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorLatches in frequecny divider using fsm implementation
I am new to verilog and HDL. I want to implement a N-frequency divider, which count clock ticks (pos and neg) and start the counting mechanism from the first rising edge of the input clk. In a...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Hi Tricky, thank you for your reply. I have seen some code examples where the signals in sensitivity list are written without any edge statements. Such code can be synthesized ? Why quartus doesn't raise any error if such implementation is not compatible with FPGAs? --- Quote End --- Thats because those blocks will describe assignments for the variables in ALL paths through the block (ie. assigned in all ifs and else), so no latches are created.
