Latch quartus

Hi,

It would be helpful if you could publish your source code (Verilog, VHDL) etc

Thanks

you should add an asynchronous reset to your entity, instead of trying set initial values to signals..

Anyway, Quartus 6 doesn't support this feature, Quartus 7 doe's.

her is the Code

library ieee ;

use ieee.std_logic_1164.all;

entity D_latch is

port( data_in: in std_logic;

enable :in std_logic;

q : out std_logic:='0'

);

end D_latch;

architecture behv of D_latch is

begin

process(data_in, enable)

begin

if (enable='1') then

q <= data_in;

end if;

end process;

--- Quote Start ---

you should add an asynchronous reset to your entity, instead of trying set initial values to signals..

Anyway, Quartus 6 doesn't support this feature, Quartus 7 doe's.

--- Quote End ---

ok

is already done.

but they already know why Altera makes for something Latch

and not with Flipflop ?

thanks

Hi,

I believe there is some confusion here...

Firstly, a latch implies that there is no clock input and so the design is asynchronous anyway. I don't see how the latch will infer input data from asynchronous input unless you make direct wiring...

Secondly, with RTL design methodology, you better avoid using latches altogether. I have been using edge-triggered flipflops only(for the last 10 years!!). I don't think any FPGA engineer will dare use asynchronous design at any point in their design. ASIC may be. I understand a new very fast FPGA has been announced that uses asynchronous internal architecture but appears as synchronous from the desiger's perspective.

Thirdly, the initial condition of '0' is only relevant to a simulation model and is a trivial tool-dependant issue.

Regards